Computer Systems · Computer Structure

CS7 — Fetch-Execute Cycle

📅 Thu 13 Aug 2026 · P3+P4 (double)

⏱ ~90 minutes

Learning intentions

I can describe the three stages of the fetch-execute cycle: fetch, decode, execute
I can state the purpose of the key registers used during the cycle: PC, MAR, MDR, IR
I can trace the movement of data between registers during the fetch stage in the correct order
I can explain what the control unit does during the decode and execute stages

Success criteria

I can state that the PC holds the address of the next instruction to be fetched
I can describe the fetch stage in order: PC → MAR, memory → MDR, MDR → IR, PC incremented
I can distinguish between MAR (holds an address) and MDR (holds data or an instruction)
I can explain what happens during the execute stage for arithmetic, memory access, and branch instructions

Warm up — recap from CS6

Answer from memory · check when done

What does ALU stand for?

When the CPU reads data from RAM, which bus carries the memory address to be accessed?

Data bus

Incorrect — the data bus carries the actual data or instruction once the address has been located.

Control bus

Incorrect — the control bus carries timing and control signals (e.g. read/write commands), not addresses.

Address bus

Correct — the address bus carries the memory address from the CPU (via the MAR) to the RAM.

Incorrect — there is no "register bus" in the standard von Neumann architecture.

Name the processor component that interprets instructions and coordinates all other components.

Key vocabulary

Fetch-execute cycle

The continuous repeating process by which the processor fetches an instruction from memory, decodes it, then executes it

Program Counter (PC)

A register that holds the memory address of the next instruction to be fetched

Memory Address Register (MAR)

A register that holds the address in memory currently being accessed — connected to the address bus

Memory Data Register (MDR)

A register that temporarily holds data or an instruction that has just been read from memory, or is about to be written to memory — connected to the data bus

Instruction Register (IR)

A register that holds the current instruction while it is being decoded and executed by the control unit

Accumulator (ACC)

A register that holds the result of an arithmetic or logic operation performed by the ALU

Decode

The stage where the control unit reads the instruction in the IR and determines what operation is required

Execute

The stage where the decoded instruction is carried out — by the ALU, memory system, or by updating the PC

Why does the processor need a cycle?

A program stored in memory is just a sequence of instructions — each one sitting at a numbered memory address. The processor has no way to run the whole program at once. Instead, it works through the instructions one at a time, repeating the same three-stage process for each: fetch the instruction from memory, decode what it means, and execute it. This repeating process is called the fetch-execute cycle (also called the fetch-decode-execute cycle).

The cycle runs billions of times per second on a modern processor. Every single instruction a program ever executes — from a simple addition to a complex function call — passes through these same three stages.

The key registers

Several specialised registers inside the processor work together to carry out the cycle. Each has a specific job and holds a specific type of content.

Processor (CPU)

PC Program Counter
Holds next address

MAR Mem. Address Reg.
Holds current address

IR Instruction Reg.
Holds current instruction

MDR Mem. Data Reg.
Holds fetched data

Control Unit Decodes instructions · coordinates all components

ALU Arithmetic & logic

ACC Holds result

Main Memory (RAM)

0LOAD 20

1ADD 21

2STORE 22

3JUMP 0

4...

Register	Holds	Connected to
PC	The memory address of the next instruction to fetch	MAR (during fetch)
MAR	The memory address currently being accessed	Address bus → RAM
MDR	The instruction or data just read from (or being written to) memory	Data bus ↔ RAM
IR	The current instruction being decoded and executed	Control Unit
ACC	The result of an ALU arithmetic or logic operation	ALU

Stage 1 — Fetch

The fetch stage retrieves one instruction from memory and places it in the IR, ready for decoding. It always happens in the same four-step order:

Step 1

PC → MAR The address in the PC is copied to the MAR

↓ MAR sends address along the address bus to RAM

Step 2

Memory → MDR The instruction at that address is fetched into the MDR via the data bus

↓ Instruction transferred from MDR into IR

Step 3

MDR → IR The instruction is copied from the MDR to the Instruction Register

↓ PC updated so the processor is ready for the next instruction

Step 4

PC incremented PC is increased by 1 — now points to the next instruction

Notice that the PC is incremented during the fetch stage, not after execution. This is important: by the time the current instruction is executing, the PC is already pointing to the next one in sequence. For branch instructions, the execute stage can then override the PC with a different address if needed.

Why MAR and MDR are separate

The MAR and MDR work as a pair connected to the system bus. The MAR always holds an address — it says "go to this location in memory." The MDR always holds data or an instruction — it carries what was found at that address, or what is about to be written there. Keeping them separate allows the processor to address memory and transfer data at the same time on different buses.

Stage 2 — Decode

The control unit reads the instruction now sitting in the IR. It decodes it — working out what type of operation is required and identifying any operands or memory addresses involved. For example, the instruction ADD 21 would be decoded as "perform an addition using the value at memory address 21."

No data moves between the CPU and memory during decode. This stage is entirely internal to the processor.

Stage 3 — Execute

The decoded instruction is carried out. What happens at this stage depends on the type of instruction:

Arithmetic or logic instruction (e.g. ADD, SUBTRACT, AND): the ALU performs the operation and stores the result in the Accumulator (ACC).
Memory read instruction (e.g. LOAD): the target address is placed in the MAR, the value at that address is fetched into the MDR, and then copied to a register or the ACC.
Memory write instruction (e.g. STORE): the target address is placed in the MAR, the data to be written is placed in the MDR, and the data bus carries it to memory.
Branch or jump instruction (e.g. JUMP, conditional branch): the PC is updated with the destination address from the instruction. The next fetch will therefore come from that address rather than the next sequential one — enabling loops and conditional execution.

After execute, the cycle begins again immediately with another fetch, using whatever value is now in the PC.

Worked examples

Example 1 — Trace the fetch stage when PC = 3

PC → MAR: The value 3 is copied from the PC to the MAR.
State after step 1: PC = 3, MAR = 3

Memory[MAR] → MDR: The MAR sends address 3 along the address bus. The instruction stored at memory address 3 (JUMP 0) is fetched and placed in the MDR.
State after step 2: MAR = 3, MDR = JUMP 0

MDR → IR: The instruction JUMP 0 is copied from the MDR to the IR.
State after step 3: MDR = JUMP 0, IR = JUMP 0

PC incremented: The PC is increased by 1, from 3 to 4.
State after step 4: PC = 4 (but this will be overridden at execute, since this is a JUMP instruction)

✓

Fetch complete. The instruction JUMP 0 is in the IR, ready for decode. PC currently holds 4.

Example 2 — What happens during execute for three different instructions

Instruction: ADD 21
The control unit sends the address 21 to the MAR. The value at memory address 21 is fetched into the MDR. The ALU adds the value in the MDR to the current value in the ACC and stores the result back in the ACC.

Instruction: STORE 22
The address 22 is placed in the MAR. The value currently in the ACC is placed in the MDR. The data bus carries the value from the MDR to memory address 22, writing it to RAM.

Instruction: JUMP 0
The destination address 0 from the instruction is loaded directly into the PC. The next fetch will therefore retrieve the instruction at memory address 0 — the program jumps back to the beginning. The incremented PC value (4) is discarded.

Example 3 — Full fetch-execute cycle trace starting at PC = 0

Fetch: PC = 0 → MAR = 0; memory[0] = LOAD 20 → MDR; MDR → IR; PC incremented to 1.

Decode: Control unit reads LOAD 20 from IR. Determines: load the value from memory address 20 into the ACC.

Execute: Address 20 → MAR; value at memory[20] → MDR; value copied to ACC. The number stored at address 20 is now in the accumulator.

✓

Cycle repeats: PC = 1, so the next instruction fetched will be from address 1 (ADD 21). The cycle runs again immediately.

Now you try

The program counter contains the value 12 before a fetch-execute cycle begins. Assume memory address 12 contains the instruction LOAD 30.

State the contents of the MAR, MDR, and IR at the end of the fetch stage, and state what value the PC now holds.

⚠️ Common mistakes — examiner feedback

Confusing MAR and MDR. MAR holds an address — it always stores a location in memory. MDR holds data or an instruction — it stores what was found at that address. A common error is writing "the instruction is copied to the MAR" — the instruction goes to the MDR first, then the IR.
Getting the fetch stage order wrong. The sequence must be: PC → MAR, then memory → MDR, then MDR → IR, then PC incremented. Reversing any step (e.g. MDR → IR before the memory fetch) loses marks. Memorise the order.
Saying the PC is incremented after execution. The PC is incremented during the fetch stage — after the instruction is safely in the IR. Many pupils write "the PC is updated after the instruction is executed" which is incorrect for normal sequential instructions.
Describing the PC as holding the "current" instruction. The PC holds the address of the next instruction to be fetched — not the current one. The current instruction is in the IR.

📝 Exam tip

The fetch-execute cycle appears in nearly every Higher Computing paper. The most common question asks you to "describe the fetch stage" — typically worth 3 to 4 marks, one mark per correct step. Write it as a numbered list and use register names (PC, MAR, MDR, IR). Vague answers like "the instruction is fetched" earn one mark at most.

The four steps to memorise — say them out loud until automatic:

PC → MAR
Memory[MAR] → MDR (instruction fetched via address bus and data bus)
MDR → IR
PC incremented by 1

Also be ready to explain what happens to the PC when a branch/jump instruction executes — the PC is overridden with the destination address rather than using the incremented value.

Task Set A

Task Set A — Higher core

Work through all questions.

What does PC stand for?

What does MAR stand for?

What does MDR stand for?

What does IR stand for?

What is the very first thing that happens at the start of the fetch stage?

The MDR is copied to the IR

Incorrect — this is step 3 of the fetch stage, not step 1. The processor cannot copy anything to the IR until it has first fetched an instruction from memory.

The contents of the PC are copied to the MAR

Correct — the address in the PC must be placed in the MAR first, so the processor knows which memory location to access.

The MAR is copied to the PC

Incorrect — data flows PC → MAR, not the other way around. The PC holds the next address; the MAR receives it.

The PC is incremented

Incorrect — the PC is incremented at the end of the fetch stage (step 4), after the instruction has been safely loaded into the IR.

At what point during the fetch-execute cycle is the Program Counter incremented?

Before the fetch stage begins

Incorrect — the PC is not incremented before the fetch. Its value at the start of fetch is the address of the instruction about to be retrieved.

During the decode stage

Incorrect — no register updates related to the PC happen during decode. Decode is entirely internal to the control unit reading the IR.

During the fetch stage

Correct — the PC is incremented as the final step of fetch (after MDR → IR), so it is already pointing to the next instruction before execute begins.

After the execute stage

Incorrect — the PC is updated during fetch, not after execute. This ensures it is ready for the next cycle without delay.

A7 — past paper style (1 mark)

State the purpose of the Program Counter (PC).

A8 — past paper style (2 marks)

Explain what happens during the decode stage of the fetch-execute cycle.

A9 — past paper style (4 marks)

Describe the fetch stage of the fetch-execute cycle. Give the steps in the correct order and use register names in your answer.

A10 — past paper style (2 marks)

Describe what happens to the Program Counter when a branch (jump) instruction is executed.

✅ Higher checkpoint — A9 (full fetch stage description) is the most exam-relevant question in this set. Being able to write all four steps with register names under exam conditions = ready for prelim and SQA.

Task Set B

Task Set B — Extension · Beyond the specification

A program loop runs 20 times. The loop body contains 5 instructions, plus a branch instruction at the end of each iteration to jump back to the start. How many fetch-execute cycles does the loop require in total? Show your reasoning clearly.

Explain how pipelining can improve processor performance. Why might branch instructions cause a problem in a pipelined processor?

Explain the relationship between clock speed and the fetch-execute cycle. Why might running a processor at maximum clock speed all the time be undesirable?

📁 File this in OneNote under:
Higher Computing Science → Computer Systems → CS7

📌 Teacher notes — not for pupils

Timing (~90 min):
5 min — warm up independently
5 min — key vocabulary together
5 min — why a cycle? (brief framing: "programs are sequences of instructions, processor does one at a time")
10 min — the registers: refer to the CPU diagram, ensure pupils can distinguish MAR (address) from MDR (data)
10 min — fetch stage: walk through the flow-pipeline step by step, pupils narrate back
5 min — decode and execute (quick — main focus is fetch)
10 min — worked examples together on board
5 min — Now you try (independent then reveal)
35 min — Task Set A (mostly written, circulate)
Remaining — Task Set B if time

Key teaching moment: the MAR/MDR confusion is the most common error. Emphasise: MAR = the postcode (address), MDR = the parcel (contents). Draw it on the board.

A9 is the anchor question — four marks, requires all four steps in order with register names. Pupils should be able to reproduce this from memory by the end of the lesson. Suggest they write it on a revision card.

B2 (pipelining) links forward to CS8 (performance factors) — useful to flag as a preview if time allows.